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Volumn , Issue , 2004, Pages 157-161

Contacting silicon with FIB for backside circuit edit

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIFFUSION; ELECTRIC INSULATORS; ETCHING; EXTRAPOLATION; FOCUSING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; ION BEAMS; LITHOGRAPHY; MICROPROCESSOR CHIPS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

EID: 10444220297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (9)
  • 2
    • 10444257163 scopus 로고    scopus 로고
    • United States Patent No. US 6,355,494 B1
    • R.H. Livengood et al., United States Patent No. US 6,355,494 B1 (2002).
    • (2002)
    • Livengood, R.H.1
  • 3
    • 10444252505 scopus 로고    scopus 로고
    • United States Patent No. 5,948,217
    • P. Winer, R.H. Livengood, United States Patent No. 5,948,217 (1999).
    • (1999)
    • Winer, P.1    Livengood, R.H.2
  • 5
    • 10444224571 scopus 로고    scopus 로고
    • German Patent pending, No. 103 32 877.7
    • S. Schömann et al., German Patent pending, No. 103 32 877.7
    • Schömann, S.1
  • 9
    • 10444263713 scopus 로고    scopus 로고
    • DESSIS 7.0, ISE AG, Zürich, CH (2001)
    • DESSIS 7.0, ISE AG, Zürich, CH (2001)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.