-
4
-
-
84945249779
-
On the behavioral modeling of integrated circuit output buffers
-
Princeton, NJ, Oct. 27-29
-
th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, EPEP, Princeton, NJ, pp. 281-284, Oct. 27-29, 2003.
-
(2003)
th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, EPEP
, pp. 281-284
-
-
Stievano, I.S.1
Canavero, F.G.2
Maio, I.A.3
-
5
-
-
10044261565
-
Introduction to IBIS models and IBIS model making
-
Folsom, CA, Nov. 3-4
-
A.Muranyi, "Introduction to IBIS models and IBIS model making," Folsom, CA, Nov. 3-4, 2003, (Intel course available at http://www.eda.org/pub/ ibis/training/).
-
(2003)
Intel Course
-
-
Muranyi, A.1
-
6
-
-
0029483769
-
Nonlinear black-box modeling in system identification: A unified overview
-
J. Sjöberg et al., "Nonlinear black-box modeling in system identification: a unified overview," Automatica, Vol. 31, No. 12, pp. 1691-1724, 1995.
-
(1995)
Automatica
, vol.31
, Issue.12
, pp. 1691-1724
-
-
Sjöberg, J.1
-
7
-
-
0028543366
-
Training feedforward networks with the marquardt algorithm
-
Nov.
-
M. T. Hagan, M. Menhaj, "Training feedforward networks with the marquardt algorithm," IEEE Transactions on Neural Networks, Vol. 5, N. 6, pp. 989-993, Nov. 1994.
-
(1994)
IEEE Transactions on Neural Networks
, vol.5
, Issue.6
, pp. 989-993
-
-
Hagan, M.T.1
Menhaj, M.2
-
8
-
-
0025536870
-
Improving the learning speed of 2-layer neural networks by choosing initial values of the adaptive weights
-
San Diego, CA, USA, Jun. 17-21
-
D. Nguyen, B. Widrow, "Improving the learning speed of 2-layer neural networks by choosing initial values of the adaptive weights," Proc. of the International Joint Conference on Neural Networks (IJCNN), San Diego, CA, USA, pp. 21-26, Jun. 17-21, 1990.
-
(1990)
Proc. of the International Joint Conference on Neural Networks (IJCNN)
, pp. 21-26
-
-
Nguyen, D.1
Widrow, B.2
-
9
-
-
0035309966
-
LVDS I/O Interlace for Gb/s-per-Pin Operation in 0.35 μm CMOS
-
Apr.
-
A. Boni, A. Pierazzi, D. Vecchi, "LVDS I/O Interlace for Gb/s-per-Pin Operation in 0.35 μm CMOS," IEEE Journal of Solid-State Circuits, VOL. 36, NO. 4, Apr. 2001.
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.4
-
-
Boni, A.1
Pierazzi, A.2
Vecchi, D.3
-
10
-
-
0034784788
-
An SOI CMOS LVDS driver and receiver pair
-
Kyoto, Japan, Jun. 14-16
-
B. Young, "An SOI CMOS LVDS driver and receiver pair," Proc. of the 2001 Symposium on VLSI Circuits, Kyoto, Japan, pp. 153-154 Jun. 14-16, 2001
-
(2001)
Proc. of the 2001 Symposium on VLSI Circuits
, pp. 153-154
-
-
Young, B.1
-
11
-
-
0030709081
-
LVDS I/O buffers with a controlled reference circuit
-
Portland, OR, USA, Sep. 7-10
-
T. Gabara, W. Fischer, W. Werner, S. Siegel, M. Kothandaraman, P. Metz, D. Gradl, "LVDS I/O buffers with a controlled reference circuit," Proc. of the Tenth Annual IEEE International ASIC Conference and Exhibit, Portland, OR, USA, pp. 311-315, Sep. 7-10, 1997.
-
(1997)
Proc. of the Tenth Annual IEEE International ASIC Conference and Exhibit
, pp. 311-315
-
-
Gabara, T.1
Fischer, W.2
Werner, W.3
Siegel, S.4
Kothandaraman, M.5
Metz, P.6
Gradl, D.7
|