Effect of inductance on interconnect propagation delay in VLSI circuits

Proceedings - 8th IEEE Workshop on Signal Propagation on Interconnects

Volumn , Issue , 2004, Pages 121-124

  Ligocka, A ^a   Bandurski, W ^a  

^a POZNAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; FREQUENCY DOMAIN ANALYSIS; INDUCTANCE; NATURAL FREQUENCIES;

INTERCONNECTS; ON-CHIP; PROPAGATION DELAY; VOLTAGE SOURCES;

VLSI CIRCUITS;

EID: 10044224670     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Y.I.Ismail, E.G.Friedman, Effects of inductance on the propagation delay and repeater insertion in VLSI circuits, IEEE Tran. VLSI Sys., vol. 8, No. 2, April 2000, pp. 195-206.
2. A. Deutsch et al., When are transmission-line effects important for on-chip inerconnections, IEEE Tran.on MTT., vol. 45, No. 10, Octob.1997, pp. 1836-1846.
3. K.Banerjee, A.Mehrotra, Analysis on-chip inductance effects for distributed RLC interconnects, IEEE Tran. On CAD of Integr. Circuits and Syst., vol.16, No. 8, august 2002. pp. 904-915.
4. B. Chen, H.Young, R.Luo, H.Wang, A novel method for worst-case interconnet estimation, IEEE CAS-I, vol. 50, No.6, June 2003, pp. 778-781.
5. th Workshop on Signal Propagation on Interconnects (SPI), Siena, Italy, 11-14 May 2003, pp. 163-166.