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Volumn 21, Issue 6, 2003, Pages 2352-2359
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20 nm polysilicon gate patterning and application in 36 nm complementary metal-oxide-semiconductor devices
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Author keywords
[No Author keywords available]
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Indexed keywords
ANISOTROPY;
BINDING ENERGY;
CHEMICAL BONDS;
CHEMICAL VAPOR DEPOSITION;
CMOS INTEGRATED CIRCUITS;
ELECTRON BEAM LITHOGRAPHY;
GATES (TRANSISTOR);
HIGH RESOLUTION ELECTRON MICROSCOPY;
PLASMA ETCHING;
REACTION KINETICS;
SCANNING ELECTRON MICROSCOPY;
SURFACE STRUCTURE;
TRANSMISSION ELECTRON MICROSCOPY;
X RAY PHOTOELECTRON SPECTROSCOPY;
ETCH RATES;
RESIST ASHING;
POLYSILICON;
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EID: 0942289275
PISSN: 10711023
EISSN: None
Source Type: Journal
DOI: 10.1116/1.162051410.1116/1.1620514 Document Type: Article |
Times cited : (11)
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References (12)
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