System-on-Chip Packet Processor for an Experimental Network Services Platform

GLOBECOM - IEEE Global Telecommunications Conference

Volumn 7, Issue , 2003, Pages 3933-3937

  Taylor, David ^a   Chandra, Alex ^a   Chen, Yuhua ^a   Dharmapurikar, Sarang ^a   Lockwood, John ^a   Tang, Wenjing ^a   Turner, Jonathan ^a  

^a WASHINGTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; MULTICASTING; MULTIMEDIA SYSTEMS; NETWORK PROTOCOLS; QUEUEING NETWORKS; RESEARCH LABORATORIES; SCHEDULING; SPEED CONTROL; TELECOMMUNICATION LINKS; TELECOMMUNICATION TRAFFIC; THROUGHPUT;

EXTENSIBLE NETWORK TECHNOLOGY; NETWORK SERVICES PLATFORM (NSP);

PACKET NETWORKS;

EID: 0842310789     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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8. S. Golestani, "A self-clocked fair queuing scheme for high speed applications," in Proceedings of IEEE INFOCOM, 1994.
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11. J. W. Lockwood, J. S. Turner, and D. E. Taylor, "Field programmable port extender (FPX) for distributed routing and queuing," in ACM International Symposium on Field Programmable Gate Arrays (FPGA'2000), (Monterey, CA, USA), pp. 137-144, Feb. 2000.
12. J. D. DeHart, W. D. Richard, E. W. Spitznagel, and D. E. Taylor, "The smart port card: An embedded Unix processor architecture for network management and active networking," Tech. Rep. WUCS-01-18, Applied Research Laboratory, Department of Computer Science, Washington University in Saint Louis, August 2001.