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Volumn 9, Issue 5, 2003, Pages 297-313

Real-time image processing with dynamically reconfigurable architecture

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; FIELD PROGRAMMABLE GATE ARRAYS; REAL TIME SYSTEMS;

EID: 0347410766     PISSN: 10772014     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.rti.2003.07.001     Document Type: Article
Times cited : (18)

References (17)
  • 3
    • 0346517000 scopus 로고    scopus 로고
    • Dynamically reconfigurable architectures for digital signal processing applications
    • Kluwer Academic Publisher, Dordrecth
    • Sassatelli G, Torres L, Benoit P, Cambon G, Robert M, Galy J. Dynamically reconfigurable architectures for digital signal processing applications. SoC design methodology. Kluwer Academic Publisher, Dordrecth, 2002. p. 63-74.
    • (2002) SoC Design Methodology , pp. 63-74
    • Sassatelli, G.1    Torres, L.2    Benoit, P.3    Cambon, G.4    Robert, M.5    Galy, J.6
  • 4
    • 0345886164 scopus 로고    scopus 로고
    • A dynamically reconfigurable architecture for low-power multimedia terminals
    • Kluwer Academic Publisher, Dordrecht
    • David R, Chillet D, Pillement S, Sentiyes O. A dynamically reconfigurable architecture for low-power multimedia terminals. SoC design methodology. Kluwer Academic Publisher, Dordrecht, 2002. p. 51-62.
    • (2002) SoC Design Methodology , pp. 51-62
    • David, R.1    Chillet, D.2    Pillement, S.3    Sentiyes, O.4
  • 5
    • 85030918266 scopus 로고    scopus 로고
    • AT40K FPGA with FreeRAM™, data sheet Atmel Inc.
    • AT40K FPGA with FreeRAM™, data sheet Atmel Inc., 1999.
    • (1999)
  • 6
    • 85030925795 scopus 로고
    • Xilinx. XC6200 FPGA family, data sheet. Xilinx Inc.
    • Xilinx. XC6200 FPGA family, data sheet. Xilinx Inc., 1995.
    • (1995)
  • 7
    • 0345886165 scopus 로고    scopus 로고
    • Xilinx Corporation, San Jose, CA, Virtex data sheet
    • Xilinx Corporation, San Jose, CA, Virtex data sheet, 2001.
    • (2001)
  • 14
    • 0013013396 scopus 로고    scopus 로고
    • Architectures reconfigurables dynamiquement ddies aux traitements en temps rel des signaux vido
    • Thesis, Faculty of Nancy I, France
    • Guermoud H. Architectures reconfigurables dynamiquement ddies aux traitements en temps rel des signaux vido. Thesis, Faculty of Nancy I, France, 1997.
    • (1997)
    • Guermoud, H.1
  • 15
    • 0004212135 scopus 로고    scopus 로고
    • Conception d'architectures matrielles reconfigurables dynamiquement ddies au traitement d'images temps rel
    • Thesis, Faculty of Cergy Pontoise (Jury: P. Bertin, D. Demigny, L. Kessal, M. Paidavoine, R. Tourki, S. Weber), France, July
    • Bourguiba R. Conception d'architectures matrielles reconfigurables dynamiquement ddies au traitement d'images temps rel. Thesis, Faculty of Cergy Pontoise (Jury: P. Bertin, D. Demigny, L. Kessal, M. Paidavoine, R. Tourki, S. Weber), France, July 2000.
    • (2000)
    • Bourguiba, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.