Efficient ASIC and FPGA implementations of IIR filters for real time edge detection

IEEE International Conference on Image Processing

Volumn 2, Issue , 1997, Pages 406-409

  Lorca, F G ^a   Kessal, L ^a   Demigny, D ^a  

^a UNIVERSITÉ DE CERGY PONTOISE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DIGITAL FILTERS; IMAGE QUALITY; LOGIC GATES; OPTIMIZATION; REAL TIME SYSTEMS; STORAGE ALLOCATION (COMPUTER);

DERICHE FILTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EDGE DETECTION;

EID: 0031338579     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)