Parallel Breadth-First BDD Construction

SIGPLAN Notices (ACM Special Interest Group on Programming Languages)

Volumn 32, Issue 7, 1997, Pages 145-156

  Yang, Bwolen ^a   O'Hallaron, David R ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0347306324     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/263767.263784     Document Type: Article

References (24)

1. AMZA, C., COX, A., DWARKADAS, S., HYAMS, C., LI, Z., AND ZWAENEPOEL, W. Treadmarks: Shared memory computing on networks of workstations. IEEE Computer 29, 2 (Feb 1996), 18-28.
2. ASHAR, R., AND CHEONG, M. Efficient breadth-first manipulation of binary decision diagrams. In Proceedings of the International Conference on Computer-Aided Design (November 1994), pp. 622-627.
3. BRACE, K., RUDELL, R., AND BRYANT, R. E. Efficient implementation of a BDD package. In Proceedings of the 27th ACM/IEEE Design Automation Conference (June 1990), pp. 40-45.
4. BRGLEZ, F., AND FUJIWARA, H. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In 1985 International Symposium on Circuits And Systems (1985).
5. BRYANT, R. E. Graph-based algorithms for Boolean function manipulation. In IEEE Transactions on Computers (1986), vol. C-35, pp. 8:677-691.
6. CHEN, Y.-A., AND BRYANT, R. E. Acv: An arithmetic circuit verifier. In Proceedings of the International Conference on Computer-Aided Design (November 1996), pp. 361-365.
7. CHEN, Y.-A., YANG, B., AND BRYANT, R. E. Breadth-first with depth-first BDD construction: A hybrid approach. Tech. Rep. CMU-CS-97-120, School of Computer Science, Carnegie Mellon University, 1997.
8. DRECHSLER, R., BECKER, B., AND RUPPERTZ, S. K*BMDs: a new data structure for verification. In Proceedings of European Design and Test Conference (March 1996), pp. 2-8.
9. DRECHSLER, R., SARABI, A., THEOBALD, M., BECKER, B., AND PERKOWSKI, M. A. Efficient representation and manipulation of switching functions based on ordered kronecker functional decision diagrams. In Proceedings of the 31st ACM/IEEE Design Automation Conference (June 1994), pp. 415-419.
10. GAI, S., REBAUDENGO, M., AND REORDA, M. S. A data parallel algorithm for Boolean function manipulation. In Proceedings of Fifth Symposium on Frontiers of Massively Parallel Computation (February 1995), pp. 28-34.
11. HETT, A., FRECHSLER, R., AND BECKER, B. MORE: Alternative Implementation of BDD-Packages by Multi-Operand Synthesis. In Proceedings of the European Design Automation Conference (1996).
12. JAIN, J., NARAYAN, A., COELHO, C., KHATRI, S., SANGIOVANNI-VINCENTELLI, A., AND R.K. BRAYTON, M. F. Decomposition techniques for efficient ROBDD construction. In Proceedings of the Formal Methods on Computer-Aided Design (November 1996), pp. 419-434.
13. JHA, S., LU, Y., MINEA, M., AND CLARKE, E. M. Equivalence checking using abstract BDDs. Submitted to 1997 IEEE International Conference on Computer Design, 1997.
14. KIMURA, S., AND CLARKE, E. M. A parallel algorithm for constructing binary decision diagrams. In 1990 IEEE Proceedings of the International Conference on Computer Design (Sept 1990), pp. 220-223.
15. LENOSKI, D., LAUDON, J., GHARACHORLOO, K., WEBER, W., GUPTA, A., HENNESSY, J., HOROWITZ, M., AND LAM, M. The Stanford Dash multiprocessor. IEEE Computer 25, 3 (Mar. 1992), 63-79.
16. OCHI, H., ISHIURA, N., AND YAJIMA, S. Breadth-first manipulation of SBDD of Boolean functions for vector processing. In Proceedings of the 28th ACM/IEEE Design Automation Conference (June 1991), pp. 413-416.
17. OCHI, H., YASUOKA, K., AND YAJIMA, S. Breadth-first manipulation of very large binary-decision diagrams. In Proceedings of the International Conference on Computer-Aided Design (November 1993), pp. 48-55.
18. PARASURAM, Y., STABLER, E., AND CHIN, S.-K. Parallel implementation of BDD algorithms using a distributed shared memory. In Proceedings of 27th Hawaii International Conference on Systems Sciences (January 1994), pp. 16-25.
19. RANJAN, R. K., SANGHAVI, J. V., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. Decision diagrams on network of workstations. In 1996 IEEE Proceedings of the International Conference on Computer Design (October 1996).
20. RANJAN, R. K., SANGHAVI, J. V., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. High performance BDD package based on exploiting memory hierarchy. In Proceedings of the 33rd ACM/IEEE Design Automation Conference (June 1996), pp. 635-640.
21. RUDELL, R. Dynamic variable ordering for ordered binary decision diagrams. In Proceedings of the International Conference on Computer-Aided Design (November 1993), pp. 139-144.
22. SENTOVICH, E. M., SINGH, K. J., LAVAGNO, L., MOON, C., MURGAI, R., SALDANHA, A., SAVOJ, H., STEPHAN, P. R., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI., A. L. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB/ERL M92/41, Electronics Research Lab, University of California, May 1992.
23. SOTRNETTA, T., AND BREWER, F. Implementation of an efficient parallel BDD package. In Proceedings of the 33rd ACM/IEEE Design Automation Conference (June 1996), pp. 641-644.
24. SUBHLOK, J., AND YANG, B. A new model for integrated nested task and data parallel programming. In Ninth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (June 1997). To Appear.