A Min-Cost Flow Based Detailed Router for FPGAs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 388-393

  Lee, Seokjin ^a   Cheon, Yongseok ^b   Wong, Martin D F ^c  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b University of Texas at Austin   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

FPGA routing; Lagrangian relaxation; Min cost flow algorithm

Indexed keywords

ROUTING ALGORITHMS; ROUTING CHANNELS;

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; LAGRANGE MULTIPLIERS; PROBLEM SOLVING;

ROUTERS;

EID: 0346778739     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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