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Volumn 766, Issue , 2003, Pages 265-272

Development of porous SiLK™ semiconductor dielectric resin for the 65 nm and 45 nm nodes

Author keywords

[No Author keywords available]

Indexed keywords

CURING; MORPHOLOGY; PERMITTIVITY; PORE SIZE; POROSITY; POROUS MATERIALS; REACTION KINETICS; THERMAL CYCLING; THERMAL EFFECTS;

EID: 0346308353     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (13)
  • 2
    • 26144444879 scopus 로고    scopus 로고
    • Transmission electron microscopy study of porosity and pore morphology in porous low-k dielectric resin
    • to be published
    • H. Tang, S. Rozeveld, E. Beach, J. Blackson, "Transmission Electron Microscopy Study of Porosity and Pore Morphology in Porous Low-k Dielectric Resin," to be published.
    • Tang, H.1    Rozeveld, S.2    Beach, E.3    Blackson, J.4
  • 4
    • 0347708021 scopus 로고    scopus 로고
    • Thermal shock testing is described in JEDEC standards JESD22-A106-A
    • Thermal shock testing is described in JEDEC standards JESD22-A106-A.
  • 5
    • 0347569462 scopus 로고    scopus 로고
    • Sequential process modeling for determining process-induced thermal stress in advanced Cu/low-k interconnects
    • paper E6.2
    • K. Yang, J. Waeterloos, J.-H. Im, M. Mills, "Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects," Mat. Res. Soc. Spring Meeting, 2003, paper E6.2.
    • (2003) Mat. Res. Soc. Spring Meeting
    • Yang, K.1    Waeterloos, J.2    Im, J.-H.3    Mills, M.4
  • 8


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.