Integration of retiming with architectural floorplanning

Integration, the VLSI Journal

Volumn 29, Issue 1, 2000, Pages 25-43

  Tabbara, Abdallah ^a   Tabbara, Bassam ^a   Brayton, Robert K ^a   Newton, Richard A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; POLYNOMIALS; PROBLEM SOLVING;

ARCHITECTURE FLOORPLANNING; RETIMING;

VLSI CIRCUITS;

EID: 0034159552     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(99)00021-8     Document Type: Article

References (15)

1. Eory F., Systems to Silicon Design: Methodology for Deep Sub-micron ASICs, SuperCon, 1997.
2. Sylvester D., Keutzer K., Getting to the bottom of deep submicron, Proceedings of the International Conference on Computer Aided Design, 1998, pp. 203-211.
3. Otten R.H.J.M., Brayton R.K., Planning for Performance, Proceedings of the Design Automation Conference, 1998, pp. 122-127.
4. C.E. Leiserson, J.B. Saxe, Retiming synchronous circuitry. Algorithmica. 6:1991;5-35.
5. N. Shenoy, R. Rudell, Efficient implementation of retiming, Proceedings of the International Conference on Computer Aided Design, 1994, pp. 226-233.
6. D.B. Deokar, S.S. Sapatnekar, A fresh look at retiming via clock skew optimization, Proceedings of the 32nd Design Automation Conference, 1995, pp. 310-315.
7. N. Maheshwari, S.S. Sapatnekar, An improved algorithm for minimum-area retiming, Proceedings of the 34th Design Automation Conference, 1997, pp. 2-7.
8. Orlin J.B. A faster strongly polynomial minimum cost flow algorithm. Oper. Res. 41(2):1993;338-350.
9. Pinto Y., Shamir R. Efficient algorithms for minimum-cost flow problems with piecewise-linear convex costsD. Algorithmica. 11:1994;256-277.
10. Alur R., Timed Automata, NATO-ASI Summer School on Verification of Digital and Hybrid Systems, 1998.
11. Sentovich E., Sequential Circuit Synthesis at the Gate Level, Ph.D. Thesis, UC Berkeley, 1993 (Chapter 5).
12. Tabbara A., Brayton R.K., Newton A.R., Retiming for DSM with area-delay trade-offs and delay constraints, Proceedings of the Design Automation Conference, 1999, pp. 725-730.
13. Tabbara A., Tabbara B., Inter-module Interconnect Strategy for System on Chip Applications, University of California at Berkeley Electronics Research Laboratory, Memorandum No. UCB/ERL M99/45, September 1, 1999.
14. Ji-Ren Y., Karlsson I., Svensson C. A true single-phase-clock dynamic CMOS circuit technique. IEEE J. Solid State Circuits. J-SC-22(5):1987;899-901.
15. Yuan J., Svensson C., Fast and robust CMOS double pipeline using new TSPC multiplexer and demultiplexer, International Conference on ASIC, 1996.