A Library Compatible Driver Output Model for On-Chip RLC Transmission Lines

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 1, 2004, Pages 128-136

  Agarwal, Kanak ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Inductance; Interconnect; Timing

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC LOADS; ELECTRIC RESISTANCE; INDUCTANCE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; REFLECTION; SIMULATORS; WAVEFORM ANALYSIS;

INDUCTIVE EFFECTS; INFLECTION POINTS; SLEW RATES;

ELECTRIC LINES;

EID: 0345869797     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.819889     Document Type: Article

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