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Volumn 36, Issue 4, 2003, Pages 27-34+4

The softening of hardware

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SYSTEMS PROGRAMMING; EMBEDDED SYSTEMS; PROBLEM SOLVING; PROGRAM DEBUGGING; PROGRAM PROCESSORS; SYSTEMS ANALYSIS;

EID: 0345352843     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2003.1193225     Document Type: Review
Times cited : (35)

References (12)
  • 1
    • 85008059061 scopus 로고    scopus 로고
    • Origin of the term software: Evidence from the JSTOR electronic journal archive
    • Apr.-June
    • F.R. Shapiro, "Origin of the Term Software: Evidence from the JSTOR Electronic Journal Archive," IEEE Annals of the History of Computing, Apr.-June 2000, p. 69.
    • (2000) IEEE Annals of the History of Computing , pp. 69
    • Shapiro, F.R.1
  • 2
    • 16244407568 scopus 로고    scopus 로고
    • Automatic architectural synthesis of VLIW and EPIC processors
    • IEEE CS Press
    • S. Aditya, B.R. Rau, and V. Kathail, "Automatic Architectural Synthesis of VLIW and EPIC Processors," IEEE/ACM Int'l Symp. System Synthesis, IEEE CS Press, 1999, pp. 107-113.
    • (1999) IEEE/ACM Int'l Symp. System Synthesis , pp. 107-113
    • Aditya, S.1    Rau, B.R.2    Kathail, V.3
  • 3
    • 0032676533 scopus 로고    scopus 로고
    • Customized instruction sets for embedded processors
    • IEEE CS Press
    • J. Fischer, "Customized Instruction Sets for Embedded Processors," Proc. Design Automation Conf., IEEE CS Press, 1999, pp. 253-258.
    • (1999) Proc. Design Automation Conf. , pp. 253-258
    • Fischer, J.1
  • 4
    • 0033884908 scopus 로고    scopus 로고
    • Xtensa: A configurable and extensible processor
    • R. Gonzalez, "Xtensa: A Configurable and Extensible Processor," IEEE Micro, vol. 20, no. 2, 2000, pp. 60-70; see also www.tensilica.com.
    • (2000) IEEE Micro , vol.20 , Issue.2 , pp. 60-70
    • Gonzalez, R.1
  • 7
    • 0030171884 scopus 로고    scopus 로고
    • FPGA and CPLD architectures: A tutorial
    • S. Brown and J. Rose, "FPGA and CPLD Architectures: A Tutorial," IEEE Design & Test of Computers, vol. 13, no. 2, 1996, pp. 42-57.
    • (1996) IEEE Design & Test of Computers , vol.13 , Issue.2 , pp. 42-57
    • Brown, S.1    Rose, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.