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Volumn 3, Issue , 1999, Pages 1401-1405

SOM on multi-FPGA ISA board-hardware aspects

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMAL MAPPING; INTEGRATED CIRCUIT DESIGN; NEURAL NETWORKS; SELF ORGANIZING MAPS;

EID: 0345251995     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1999.814431     Document Type: Conference Paper
Times cited : (1)

References (17)
  • 4
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    • Issues in the design of high performance SIMD architectnres
    • Angust
    • J. D. Aflen and D. E. Schimmel "Issues in the Design of High Performance SIMD Architectnres" ,IEEE Trans. on PADS,pp. 818-829, Vol. 7, No. S,Angust 1996.
    • (1996) IEEE Trans. on PADS , vol.7 , Issue.5 , pp. 818-829
    • Aflen, J.D.1    Schimmel, D.E.2
  • 7
    • 84892187255 scopus 로고
    • Hardware oriented models for VLSI implementation of SOM
    • Jnne Springer
    • B. Brio and J. Alberto ,"Hardware Oriented Models for VLSI Implementation of SOM ", in Proc. of IWANN'95,pp. 712-719 ,Jnne 1995,LNCS 930, Springer.
    • (1995) Proc. of IWANN'95, LNCS 930 , pp. 712-719
    • Brio, B.1    Alberto, J.2
  • 10
    • 0031100792 scopus 로고    scopus 로고
    • Modified self-Organizing feature map algorithms for efficient digital hardware implementation
    • march
    • P. Ienne, P. Thiran, and N. Vassilas, "Modified Self-Organizing Feature Map Algorithms for Efficient Digital Hardware Implementation", IEEE Transactions on neural networks, pp. 3l5-329, vol. 8, no. 2, march 1997.
    • (1997) IEEE Transactions on Neural Networks , vol.8 , Issue.2 , pp. 3l5-329
    • Ienne, P.1    Thiran, P.2    Vassilas, N.3
  • 11
    • 0026838206 scopus 로고
    • CANCLIONA Fast Field-Programmable gate array implementation of a connectionist classifier
    • March
    • C. E. Cox and W. Ekkehard Blanz,"CANCLIONA Fast Field-Programmable Gate Array Implementation of a Connectionist Classifier" IEEE Journal of Solid State Circuits, Vol. 27, No. 3, March 1992.
    • (1992) IEEE Journal of Solid State Circuits , vol.27 , Issue.3
    • Cox, C.E.1    Ekkehard Blanz, W.2
  • 12
    • 84940398220 scopus 로고    scopus 로고
    • Virtual Computer Corporation
    • Virtual Computer Corporation, "Virtual ISA Proto Board User Guide", 1996. (www. vcc. com)
    • (1996) Virtual ISA Proto Board User Guide
  • 15
    • 0011188434 scopus 로고    scopus 로고
    • Xilinx Corp. Application Brief XBRFO15 1. 0 November
    • Xilinx Corp. ,"Speed Metrics for High Performance FPGAs", Application Brief XBRFO15 1. 0, November 1997.
    • (1997) Speed Metrics for High Performance FPGAS
  • 17
    • 0032047685 scopus 로고    scopus 로고
    • Integrating HDL synthesis and partitionning for high density mnlti-FPGA Designs
    • April-Jnne
    • W. Fang and A. Wn,"Integrating HDL Synthesis and Partitionning for High Density Mnlti-FPGA Designs", IEEE Design and Test of Computers. April-Jnne 1998.
    • (1998) IEEE Design and Test of Computers
    • Fang, W.1    Wn, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.