Issues in the design of high performance SIMD architectures

IEEE Transactions on Parallel and Distributed Systems

Volumn 7, Issue 8, 1996, Pages 818-829

  Allen, James D ^a,b   Schimmel, David E ^a,b  

^a IEEE

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Caches; Data parallel; MasPar; Pipelining; SIMD

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; COMPUTER SOFTWARE; MICROCOMPUTERS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; SYNCHRONIZATION;

DATA PARALLEL; DIRECT ONLY DATA CACHE; MASPAR; PROCESSING ELEMENTS; SINGLE INSTRUCTION MULTIPLE DATA ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 0030216064     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.532113     Document Type: Article

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