Automated robust design and optimization of integrated circuits by means of penalty functions

AEU - International Journal of Electronics and Communications

Volumn 57, Issue 1, 2003, Pages 47-56

  Bürmen, Árpád ^a   Strle, Drago ^a   Bratkovič, Franc ^a   Puhan, Janez ^a   Fajfar, Iztok ^a   Tuma, Tadej ^a  

^a UNIVERSITY OF LJUBLJANA   (Slovenia)

Author keywords

Analog IC; CAD; Circuit sizing; Optimization; Penalty function

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; DIFFERENTIAL AMPLIFIERS; FUNCTIONS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

CONSTRAINED OPTIMIZATION; PENALTY FUNCTIONS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0345016291     PISSN: 14348411     EISSN: 16180399     Source Type: Journal    
DOI: 10.1078/1434-8411-54100139     Document Type: Article

References (22)

1. Gielen, G.G.E; Rutenbar, R.A.: Computer-aided design of analog and mixed-signal integrated circuits. Proceedings of the IEEE 88 (2000), 1825-1854.
2. del Mar Hershenson, M.; Boyd, S.P.; Lee, T.H.: Optimal design of a CMOS op-amp via geometric programming. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 20 (2001), 1-21.
3. Phelps, R.; Krasnicki, M.; Rutenbar, R.A.; Carley, L.R.; Hellums, J.R.: Anaconda: robust synthesis of analog circuits via stochastic pattern search. Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, San Diego, CA, USA, 1999, 567-570.
4. Krasnicki, M.; Phelps, R.; Rutenbar, R.A.; Carley, L.R.: Maelstrom: efficient simulation-based synthesis for custom analog cells, Proceedings 1999 Design Automation Conference, New Orleans, LA, USA, 1999, 945-950.
5. Phelps, R.; Krasnicki, M.; Rutenbar, R.A.; Carley, L.R.; Hellums, J.R.: Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 19 (2000), 703-717.
6. Schwencker, R.; Schenkel, F.; Gräb, H.; Antreich, K.: The generalized boundary curve - a common method for automatic nominal design and centering of analog circuits, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000, Los Alamitos, CA, USA, 2000, 42-47.
7. Aftab, S.A.; Styblinski, M.A.: IC variability minimization using a new Cp and Cpk based variability/performance measure. Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, London, UK, 1994. 149-152.
8. Keramat, M.; Kielbasa, R.: Optomega: an environment for analog circuit optimization, ISCAS '98 Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA, USA, 1998, 122-125.
9. Abdel-Malek, H.; Hassan, A.: The ellipsoidal technique for design centering and region approximation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 10 (1991), 1006-1014.
10. Dharchoudhury, A.; Kang, S. M.: Worst-case analysis and optimization of VLSI circuit performances, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 14 (1995), 481-492.
11. Krishna, K.; Director, S.W.: The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 14 (1995), 1557-1568.
12. Quarles, T.; Newton, A.R.; Pederson, D.O.; Sangiovanni-Vincentelli, A.: Spice3 version 3f4 user's manual. Berkeley, CA, USA: University of California, 1989.
13. Lewis, R.M.; Torczon, V.; Trosset, M.W.: Direct search methods: then and now. Journal of Computational and Applied Mathematics 124 (2000), 191-207.
14. Gay, P.R.; Hurst, P.J.; Lewis, S.H.; Meyer, R.G.: Analysis and design of analog integrated circuits. New York, USA: John Wiley & Sons, 2001.
15. Gräb, H.; Zizala, S.; Eckmüller, J.; Antreich, K.: The sizing rules method for analog integrated circuit design. IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001, San Jose, CA, USA, 2001. 343-349.
16. Conn, A.R.; Gould, N.I.M.; Toint, P.L.: Trust-region methods. Philadelphia, USA: SIAM, 2000.
17. Puhan, J.; Tuma, T.: Optimization of analog circuits with Spice 3f4. Proceedings of 1997 European Conference on Circuit Theory and Design (ECCTD'97). Vol. 1, Budapest, Hungary, 1997. 177-180.
18. Puhan, J.; Tuma, T.; Fajfar, I.: Optimisation methods in Spice: a comparison, Proceedings of European Conference on Circuit Theory and Design. ECCTD'99. Vol. 2, Stresa, Italy, 1999, 1279-1282.
19. Box, M.J.: A new method of constrained optimization and a comparison with other methods. Computer Journal 8 (1965), 42-52.
20. Shah, A.H.: Technology migration of a high performance CMOS amplifier using an automated front-to-back analog design flow. Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings of Designers' Forum, Paris, France, 2002. 224-229.
21. Dennis, Jr., J.E.; Torczon, V.: Parallel implementations of the Nelder-Mead simplex algorithm for unconstrained optimization. Proceedings of the SPIE, Vol. 880, Los Angeles, CA, USA, 1988. 187-191.
22. Coetzee, L.; Botha, E.C.: The parallel downhill simplex algorithm for unconstrained optimisation, Concurrency: Practice and Experience 10 (1998), 121-137.