Interconnect strategies for deep submicron CMOS manufacture

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn 2000-January, Issue , 2000, Pages 413-418

  Mark, C ^a   Rose, K ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Chip scale packaging; Clocks; Conducting materials; Frequency estimation; Guidelines; Inductance; Internet; Logic; Manufacturing processes; Wiring

Indexed keywords

CHIP SCALE PACKAGES; CLOCKS; ELECTRIC WIRING; FREQUENCY ESTIMATION; GATEWAYS (COMPUTER NETWORKS); INDUCTANCE; INTERNET; MANUFACTURE; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MANUFACTURE;

CHIP-SCALE PACKAGING; CONDUCTING MATERIALS; GUIDELINES; LOGIC; MANUFACTURING PROCESS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 0344667950     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2000.902620     Document Type: Conference Paper

References (5)

1. R. Mangaser, C. Mark, K. Rose, 'Interconnect Constraints on BEOL Manufacturing', IEEE/SEMI ASMC Proceedings, pp. 304-308, 1999.
2. B.M. Geuskens, K. Rose, "Modeling Microprocessor Performance", Kluwer Academic Publishers, 1998.
3. Y.I. Ismail, E.G. Friedman, J.L. Neves, 'Figures of Merit to Characterize the Importance of On-chip Inductance' IEEE Trans. VLSI Systems, 7/4, pp. 1-8, Dec. 1999.
4. th Anniversary Conference on Advanced Research in VLSI, pp. 114-122, 1999.
5. V. Blaschke, G. Bersuker, et al., 'Integration Aspects for Damascene Copper Interconnect in Low K Dielectric', Proc. IITC, pp. 154-156, 1998.