A threshold logic full adder based on resonant tunneling transistors

European Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 428-431

  Pacha, Christian ^a   Goser, Karl ^a   Brennemann, Andreas ^b   Prost, Werner ^b  

^a TU DORTMUND UNIVERSITY   (Germany)

^b UNIVERSITY OF DUISBURG ESSEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT ARCHITECTURES; COMPUTATIONAL FUNCTIONALITY; EFFICIENT IMPLEMENTATION; FULL ADDER CELLS; HETEROSTRUCTURE FIELD EFFECT TRANSISTORS; LINEAR THRESHOLD GATES; MONOLITHICALLY INTEGRATED; RESONANT TUNNELING TRANSISTORS;

MONOLITHIC INTEGRATED CIRCUITS; RESONANT TUNNELING; THRESHOLD LOGIC;

FIELD EFFECT TRANSISTORS;

EID: 0343705243     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.1998.186300     Document Type: Conference Paper

References (7)

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2. S. Cotofana. Additions Related Arithmetic Operations with Threshold Logic. PhD thesis, Laboratory of Computer Architecture and Digital Techniques (CARDIT), Faculty of Electrical Engineering, Delft University of Technology, NL, 1997.
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7. P. v. d. Wagt, A. Seabaugh, and E. Beam. RTD/HFET Low Standby Power SRAM Gain Cell. Technical Digest IEDM, pages 425-428,1996.