S/390 G5/G6 binodal cache

IBM Journal of Research and Development

Volumn 43, Issue 5, 1999, Pages 661-670

  Turgeon, Paul R ^a   Pak Kin, Mak ^a   Blake, Michael A ^a   Fee, Michael F ^a   Ford III, Carl B ^a   Meaney, P J ^b   Seigler, R ^b   Shen, W W ^b  

^a IBM   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CLIENT SERVER COMPUTER SYSTEMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; FAULT TOLERANT COMPUTER SYSTEMS; INFORMATION MANAGEMENT;

BINODAL CACHE; MEMORY HIERARCHY;

BUFFER STORAGE;

EID: 0343517441     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.435.0661     Document Type: Article

References (9)

1. P. Mak, M. A. Blake, C. C. Jones, G. E. Strait, and P. R. Turgeon, "Shared-Cache Clusters in a System with a Fully Shared Memory," IBM J. Res. Develop. 41, No. 4/5, 429-448 (1997).
2. M. A. Check and T. J. Slegel, "Custom S/390 G5 and G6 Microprocessors," IBM J. Res. Develop. 43, No. 5/6. 671-680 (1999, this issue).
3. G. Northrop, R. Averill, K. Barkley, S. Carey, Y. Chan, Y. H. Chan, M. Check, D. Hoffman, W. Huott, B. Krumm, C. Krygowski, J. Liptay, M. Mayo, T. McNamara, T. McPherson, E. Schwarz, L. Sigal, T. Slegel, C. Webb, D. Webber, and P. Williams, "600MHz G5 S/390 Microprocessor," International Solid-State Circuits, Conference Digest of Technical Papers, February 1999, pp. 88-89.
4. T. J. Siegel, R. M. Averill III, M. A. Check, B. C. Giamei, B. W. Krumm, C. A. Krygowski, W. H. Li, J. S. Liptay, J. D. MacDougall, T. J. MacPherson, J. A. Navarro, E. M. Schwarz, K. Shum, and C. F. Webb, "IBM's S/390 G5 Microprocessor Design," IEEE Micro 19, No. 2, 12-23 (March/April 1999).
5. P. Turgeon, P. Mak, D. Plass, M. Blake, M. Fee, M. Fischer, C. Ford, G. Holmes, K. Jackson, C. Jones, K. Kark, F. Malgioglio, P. Meaney, E. Pell, W. Scarpero, A. E. Seigler, W. Shen, G. Strait, G. Van Huben, G. Wellwood, and A. Zuckerman, "A Storage Hierarchy to Support a 600 MHz S/390 G5 Microprocessor," International Solid-State Circuits Conference Digest of Technical Papers, February 1999, pp. 90-91.
6. P. Mak, M. Blake, and G. Van Huben, "High Speed Remote Storage Cluster Interface Controller," filed 9/23/97, U.S. patent pending.
7. P. Meaney, G. Ingenio, T. McNamara, and P. Muench, "Method for Supporting 1 1/2 Cycle Data Paths via PLL Based Clock System," filed 2/13/97, U.S. patent pending.
8. P. Mak, P. Meaney, W. Shen, and G. Strait, "Computer System UE Recovery Logic," filed 11/6/97, U.S. patent pending.
9. P. Mak, M. Blake, M. Fee, C. Jones, and G. Strait, "Computer System Deadlock Request Resolution," filed 2/2/98, U.S. patent pending.