Shared-cache clusters in a system with a fully shared memory

IBM Journal of Research and Development

Volumn 41, Issue 4-5, 1997, Pages 429-448

  Mak, P ^a,b,c,d   Blake, M A ^a,b,e   Jones, C C ^a,b,f   Strait, G E ^a,b,e,g   Turgeon, P R ^a,b,e  

^a IBM   (United States)

^b S/390 Development Organization   (United States)

^c POLYTECHNIC UNIVERSITY   (United States)

^d UNION COLLEGE   (United States)

^e RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^f MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^g Hudson Valley Community College   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS;

SHARED CACHE CLUSTERS;

BUFFER STORAGE;

EID: 0031177026     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0429     Document Type: Article

References (10)

1. G. Doettling, K. J. Getzlaff, B. Leppla, W. Lipponer, T. Pflueger, T. Schlipf, D. Schmunkamp, and U. Wille, "S/390 Parallel Enterprise Server Generation 3: A Balanced System and Cache Structure," IBM J. Res. Develop. 41, 405-428 (1997, this issue).
2. K. J. Getzlaff, H. W. Tast, U. Wille, B. Leppla, G. Doettling, W. W. Shen, P. Mak, K. N. Langston, and K. M. Jackson, "Shared Cache Memory Device," filed 7/19/95, U.S. patent pending.
3. C. F. Webb and J. S. Liptay, "A High-Frequency Custom CMOS S/390 Microprocessor," IBM J. Res. Develop. 41, 463-473 (1997, this issue).
4. P. Mak, C. B. Ford, and M. A. Blake, "Computer Architecture Incorporating Processor Clusters and Hierarchical Cache Memories," filed 8/15/96, U.S. patent pending.
5. L. Sigal, J. D. Warnock, B. W. Curran, Y. H. Chan, P. J. Camporese, M. D. Mayo, W. V. Huott, D. R. Knebel, C. T. Chuang, J. P. Eckhardt, and P. T. Wu, "Circuit Design Techniques for the High-Performance CMOS IBM S/390 Parallel Enterprise Server G4 Microprocessor," IBM J. Res. Develop. 41, 489-503 (1997, this issue).
6. B. J. O'Leary and A. J. Sutton, "Dynamic Cache Line Delete," IBM Tech. Disclosure Bull., p. 489 (1989).
7. P. Mak and P. J. Meaney, "Resource Arbitration System with Resource Checking and Lockout," U.S. Patent 5,564,062, 1996.
8. P. Mak, L. J. Clark, S. T. Comfort, C. C. Jones, B. M. Bean, A. E. Bierce, and N. T. Christensen, "Interlock for Controlling Processor Ownership of Pipelined Data for a Store-In Cache," U.S. Patent 5,490,261, 1996.
9. Jim Handy, The Cache Memory Book, Academic Press, Inc., San Diego, 1993.
10. P. Mak, W. W. Shen, C. K. Shum, C. F. Webb, S. G. Glassen, and J. R. Easton, "A Mechanism for Locking a Unit of Storage in a Multiprocessor System," filed 3/31/95, U.S. patent pending.