Random-access data storage components in customized architectures

IEEE Design and Test of Computers

Volumn 18, Issue 3, 2001, Pages 40-43+45

  Nachtergaele, Lode ^b   Catthoor, Francky ^a   Kulkarni, Chidamber ^b  

^a IMEC   (Belgium)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; DATA TRANSFER; DIGITAL SIGNAL PROCESSING; MULTIPROCESSING SYSTEMS; PROM; STATIC RANDOM ACCESS STORAGE; VERY LONG INSTRUCTION WORD ARCHITECTURE;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSORS; ELECTRICALLY ALTERABLE READ ONLY MEMORY; POINTER ADDRESSED MEMORY; PROGRAMMABLE LOGIC ARRAYS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0343026457     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.922802     Document Type: Article

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