A CMOS high-speed data recovery circuit using the matched delay sampling technique

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 10, 1997, Pages 1588-1596

  Kang, Jin Ku ^a,b   Liu, Wentai ^a   Cavin III, Ralph K ^a,c  

^a North Carolina State University   (United States)

^b Inha University   (South Korea)

^c SEMICONDUCTOR RESEARCH CORPORATION   (United States)

Author keywords

Clock and data recovery; DLL; NRZ data; Transceiver

Indexed keywords

DIGITAL CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING;

CMOS HIGH SPEED DATA RECOVERY CIRCUIT; DEMULTIPLEXING DATA RECOVERY CIRCUIT; DIGITAL PHASE CONTROL CIRCUIT; MATCHED DELAY SAMPLING TECHNIQUE;

CMOS INTEGRATED CIRCUITS;

EID: 0031256976     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.634670     Document Type: Article

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