A 1.25Gb/s CMOS receiver core with plesiochronous clocking capability for asynchronous burst data acquisition

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 254-255

  Yoshikawa, T ^a   Yoshida, T ^a   Ebuchi, T ^a   Yamauchi, H ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DATA ACQUISITION; FLIP FLOP CIRCUITS; LSI CIRCUITS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; TIMING CIRCUITS;

PLESIOCHRONOUS CLOCKING;

TRANSCEIVERS;

EID: 0034430995     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A O.6μm CMOS 4Gb/s transceiver with data recovery using oversampling
2. An integratable 1-2.5Gb/s low jitter CMOS transceiver with built in self test capability
3. A 2B parallel 1.25Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking
4. A 156Mb/s CMOS clock recovery circuit for burst-mode transmission
5. 150/30Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection
6. 3.5Gb/s × 4-Ch Si bipolar LSIs for optical interconnections