Software caching using dynamic binary rewriting for embedded devices

Proceedings of the International Conference on Parallel Processing

Volumn 2002-January, Issue , 2002, Pages 621-630

  Huneycutt, C M ^a   Fryman, J B ^a   Mackenzie, K M ^a  

^a Georgia Institute of Technology   (United States)

Author keywords

Calibration; Cellular phones; Costs; Embedded software; Embedded system; Hardware; Memory management; Network servers; Poles and towers; Software systems

Indexed keywords

BINS; CACHE MEMORY; CALIBRATION; CELLULAR TELEPHONES; COMPUTER HARDWARE; COSTS; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; HARDWARE; MOBILE PHONES; TELEPHONE SETS;

CELLULAR PHONE; MEMORY MANAGEMENT; NETWORK SERVER; POLES AND TOWERS; SOFTWARE SYSTEMS;

CELLULAR TELEPHONE SYSTEMS;

EID: 0242400304     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2002.1040920     Document Type: Conference Paper

References (16)

1. D. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. In Journal of Instruction Level Parallelism, pages 248-261, 2000.
2. V. Bala, E. Duesterwakd, and S. Banerjia. Dynamo: A Transparent Dynamic Optimization System. In PLDI, 2000.
3. R. Bedichek. Talisman-2 - A Fugu System Simulator. http://bedichek.org/robert/talisman2/, August 1999.
4. R. F. Cmelik and D. Keppel. Shade: A Fast Instruction-Set Simulator for Execution Profiling. CSE 93-06-06, University of Washington, 1993.
5. J. B. Fryman, C. M. Huneycutt, and K. M. Mackenzie. Investigating a SoftCache via Dynamic Rewriting. In 4th Workshop on Feedback-Directed and Dynamic Optimization, December 2001.
6. E. G. Hallnor and S. K. Reinhardt. A Fully Associative Software-Managed Cache Design. In Proceedings of the 27th Annual International Symposium on Computer Architecture, 2000.
7. R. J. Hookway and M. A. Herdeg. DIGITAL FX!32: Combining Emulation and Binary Translation. Digital Technical Journal, 9(1), 1997.
8. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In MICRO-30, 1997.
9. M. Margala. Low-Power SRAM Circuit Design. In Proceedings of IEEE International Workshop on MemoryTechnology, Design and Testing, pages 115-122, 1999.
10. J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, G. W. Hoeppner, D. Kruckmyer, T. H. Lee, P. C. M. Lin, L. Madden, D. Murray, M. H. Pearce, S. Santhanam, K. J. Synder, R. Stephany, and S. C. Thierauf. A 160-MHz, 32-b, 0.5-W W RISC Microprocessor. In IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996.
11. C. A. Moritz, M. Frank, W. Lee, and S. Amarasinghe. Hot Pages: Software Caching for Raw Microprocessors. MIT-LCS-TM 599, Massachusetts Institute of Technology, 1999.
12. E. Rotenberg, S. Bennett, and J. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. In Proceedings of the 29th Annual International Symposium on Microarchitecture, pages 24-34, 1996.
13. D. J. Scales, K. Gharachorloo, and C. A. Thekkath. Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory. In Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 174-185, October 1996.
14. E. G. Sirer, R. Grimm, A. J. Gregory, and B. N. Bershad. Design and Implementation of a Distributed Virtual Machine for Networked Computers. In Proceedings of the 17th ACM Symposium on Operating Systems Principles, pages 202-216, 1999.
15. E. Witchel and M. Rosenblum. Embra: Fast and Flexible Machine Simulation. In Proceedings of ACM SIGMETRICS '96: Conference on Measurement and Modeling of Computer Systems, 1996.
16. H. Zhou, M. Toburen, E. Rotenberg, and T. Conte. Adaptive Mode Control: A Static-Power-Efficient Cache Design. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2001.