Fast on-chip inductance extraction of VLSI including angled interconnects

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E86-A, Issue 4, 2003, Pages 841-845

  Kurokawa, Atsushi ^a   Hachiya, Kotaro ^b   Sato, Takashi ^c   Tokumasu, Kazuya ^a   Masuda, Hiroo ^a  

^a STARC   (Japan)

^b NEC CORPORATION   (Japan)

^c HITACHI LTD   (Japan)

Author keywords

Geometric mean distance; Inductance; Parasitic extraction; Skin effect; VLSI interconnect

Indexed keywords

CALCULATIONS; COMPUTATIONAL GEOMETRY; COMPUTER SIMULATION; DIELECTRIC MATERIALS; EQUIVALENT CIRCUITS; ERROR ANALYSIS; INDUCTANCE; INTEGRATED CIRCUIT LAYOUT; PROBLEM SOLVING; SKIN EFFECT; THREE DIMENSIONAL;

GEOMETRIC MEAN DISTANCE; PARASITIC EXTRACTION; PARTIAL ELEMENT EQUIVALENT CIRCUIT;

VLSI CIRCUITS;

EID: 0142217387     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Letter

References (9)

1. M. Kamon, M.J. Tsuk, and J. White, "FASTHENRY: A multipole accelerated 3D inductance extraction program," IEEE Trans. Microw. Theory Tech., vol.42, no.9, pp.1750-1758, Sept. 1994.
2. Raphael version 2000.4, Avant! Corporation.
3. F.W. Grover, Inductance Calculations: Working Formulas and Tables, Dover Publications, New York, 1946.
4. Y.-C. Lu, M. Celik, T. Young, and L.T. Pileggi, "Min/max on-chip inductance models and delay metrics," Proc. ACM/IEEE DAC., pp.341-346, June 2001.
5. G. Zhong, C.-K. Koh, and K. Roy, "A twisted-bundle layout structure for minimizing inductive coupling noise," Proc. IEEE/ACM ICCAD, pp.406-411, Nov. 2000.
6. X Initiative, http://www.xinitiative.org/.
7. E. Ruehli, "Inductance calculations in a complex integrated circuit environment," IBM Journal of Research and Development, pp.470-481, Sept. 1972.
8. C.-K. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect analysis and synthesis, John Wiley & Sons, 2000.
9. "International technology roadmap for semiconductors," SIA Rep., 1999.