Eigen-signatures for regularity-based IDDQ testing

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 289-294

  Okuda, Y ^a  

^a SONY CORPORATION   (Japan)

Author keywords

Circuit testing; Electrical capacitance tomography; Electronic mail; Performance evaluation; Shape; System testing

Indexed keywords

DEFECTS; ELECTRIC IMPEDANCE TOMOGRAPHY; ELECTRONIC MAIL;

CIRCUIT TESTING; ELECTRICAL CAPACITANCE TOMOGRAPHY; PERFORMANCE EVALUATION; SHAPE; SYSTEM TESTING;

VLSI CIRCUITS;

EID: 0142174816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011155     Document Type: Conference Paper

References (6)

1. C. F. Hawkins and J. M. Soden, "Deep Submicron CMOS Current IC Testing: Is There a Future," in Design & Test of Computers, pp. 14-15, IEEE, Winter 1999.
2. Y. Okuda, "DECOUPLE: Defect Current Detection in Deep Submicron IDDQ," in ITC, pp. 199-206, IEEE, 2000.
3. DDQ Testing in Deep-Submicron Integrated Circuits," in ITC, pp. 724-729, IEEE, 1999.
4. DDQ Testing," in VTS, pp. 143-150, IEEE, 1999.
5. DDQ Testing," in ITC, pp. 101-110, IEEE, 2001.
6. P. Maxwell, P. O'Neill, R. Aitken, R. Dudley, N. Jaarsma, M. Quach, and D. Wiseman, "Current Ratios: A Self-Scaling Technique for Production IDDQ Testing," in ITC, pp. 738-746, IEEE, 1999.