Copper post-electroplating anneal: Evaluation of in-line vs. furnace anneal on layer properties

Microelectronic Engineering

Volumn 70, Issue 2-4, 2003, Pages 470-477

  Haumesser, P H ^a   Mourier, T ^a   Maitrejean S ^a   Cordeau, M ^a   Morel, T ^a   Avale, X ^b   Pollet, O ^b   Klocke, J ^b  

^a CEA LETI   (France)

^b Semitool Incorporated   (United States)

Author keywords

Anneal; Copper; Interconnects

Indexed keywords

ANNEALING; COPPER; HEAT TREATING FURNACES; MICROSTRUCTURE; THERMAL EFFECTS;

THERMAL BUDGETS;

ELECTROPLATING;

EID: 0142075260     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(03)00426-X     Document Type: Conference Paper

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