PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model - Design and Implementation of its Prototype Processor

IEICE Transactions on Information and Systems

Volumn E86-D, Issue 5, 2003, Pages 830-840

  Tanigawa, Kazuya ^a   Hironaka, Tetsuo ^a   Kojima, Akira ^a   Yoshida, Noriyoshi ^a  

^a HIROSHIMA CITY UNIVERSITY   (Japan)

Author keywords

Design and implementation; General purpose; I PARS execution model; PARS architecture; Reconfigurable architecture

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; TRANSISTORS;

RECONFIGURABLE ARCHITECTURE;

PARALLEL PROCESSING SYSTEMS;

EID: 0141903544     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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