A generalized execution model for programming on reconfigurable architectures and an architecture supporting the model

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 434-443

  Tanigawa, Kazuya ^a   Hironaka, Tetsuo ^a   Kojima, Akira ^a   Yoshida, Noriyoshi ^a  

^a HIROSHIMA CITY UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; GENERAL PURPOSE COMPUTERS; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EXECUTION MODEL; HARDWARE STRUCTURES; IDEAL PARALLEL STRUCTURES;

RECONFIGURABLE ARCHITECTURES;

EID: 79955131530     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_46     Document Type: Conference Paper

References (8)

1. H. Singh, M. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, E. M. C. Filho, "Mor-phoSys: An Integrated Reconfigurable System for Data-Parallel Computation-Intensive Applications," IEEE Transactions on Computer, Vol. 49, No.5, pp.465-481, May 2000.
2. T. J. Callahan, J. R. Hauser, J. Wawrzynek, "The Garp Architecture and C Compiler," IEEE Computer, pp62-69, Vol.33, No. 4, April 2000.
3. S. C. Goldstein, H. Scbmit, M. Budiu, S. Cadambi M. Moe, R. R. Taylor, "Pipe Rench: A Reconfigurable Architecture and Compiler," IEEE Computer, pp. 70-77, April 2000. (Pubitemid 30585676)
4. E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon, "Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial," http://brass.cs.berkeley.edu/documents/score- tutorial.pdf.
5. K. Tanigawa, T. Hironaka, N. Yoshida, "PARS Programming Model and PARS Architecture," Information Processing Society of Japan, Tech. Rep. 2000-ARC-140, pp.37-42, 2000 (in Japanese).
6. K. Tanigawa, T. Yoshida, A. Kojima, T. Hironaka, N. Yoshida, "The Detailed Design of the PARS Architecture" Information Processing Society of Japan, Tech. Rep. 2001-ARC-144, pp.31-36, 2001 (in Japanese).
7. http://www.sun.com/processors/UltraSPARC-III/specs.html
8. Akihiro Shimizu, Shoji Miyaguchi, "Fast Data Encipherment Algorithm FEAL," In David Chaum and Wyn L. Price, editors, Advances in Cryptology - EU-ROCRYPT'87, volume 304 of Lecture Notes in Computer Science, pp. 267-278. Springer-Verlag, Berlin, Heidelberg, New York, 1988.