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Volumn , Issue , 2003, Pages 291-297

Characterization of In-Process Substrate Warpage of Underfilled Flip Chip Assembly

Author keywords

[No Author keywords available]

Indexed keywords

CRACK INITIATION; FLIP CHIP DEVICES; RELIABILITY; RESIDUAL STRESSES; SENSORS; SOLDERING; ASSEMBLY; CHARACTERIZATION; CHIP SCALE PACKAGES; DELAMINATION; ELECTRONICS PACKAGING; FAILURE (MECHANICAL); INDUSTRIAL ELECTRONICS; LEAD; MANUFACTURE; SILICON; SUBSTRATES; TESTING; VEHICLES;

EID: 0141565355     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (7)
  • 4
    • 0030714913 scopus 로고    scopus 로고
    • Stresses From Flip Chip Assembly and Underfill: Mesaurements with the ATC4.1 Assembly Test Chip and Analysis by Finite Element Method
    • IEEE
    • D.W.Peterson, J.N.Sweet, S.N.Burchett, A. Hsia, "Stresses From Flip Chip Assembly and Underfill: Mesaurements with the ATC4.1 Assembly Test Chip and Analysis by Finite Element Method", Proc. 47th Electronic components and Technology Conference, IEEE, 1997, pp 134-143.
    • (1997) Proc. 47th Electronic Components and Technology Conference , pp. 134-143
    • Peterson, D.W.1    Sweet, J.N.2    Burchett, S.N.3    Hsia, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.