An Adaptive Reference Generation Scheme for 1T1C FeRAMs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 173-174

  Chandler, Trevis ^a   Sheikholeslami, Ali ^a   Masui, Shoichi ^b   Oura, Michiya ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; FERROELECTRIC DEVICES; PARTICLE BEAM TRACKING;

REFERENCE GENERATION;

RANDOM ACCESS STORAGE;

EID: 0141538196     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A. Sheikholeslami et al., "A survey of circuit innovations for ferroelectric random-access memories," Proc. of the IEEE, pp. 667-689, May 2000
2. D.J. Jung et al., "Highly manufacturable 1T1C 4Mb FRAM with novel sensing scheme," IEDM, pp. 279-282, Dec 1999
3. Y. Eslami et al., "A differential-capacitance read scheme for FeRAMs," Symp. VLSI Circuits, pp. 298-301, June 2002
4. T. Endo and S. Kawashima "Semiconductor Integrated Circuit Device" US Patent, Pub. No. US 2002/0060930, May 23, 2002