A differential-capacitance read scheme for FeRAMs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 298-301

  Eslami, Yadollah ^a   Sheikholeslami, Ali ^a   Masui, Shoichi ^b   Endo, Toru ^b   Kawashima, Shoichiro ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CAPACITORS; ELECTRONIC EQUIPMENT TESTING; FERROELECTRIC DEVICES; FERROELECTRIC MATERIALS; MICROPROCESSOR CHIPS; MOS DEVICES;

DIFFERENTIAL-CAPACITANCE READ SCHEME; FERROELECTRIC CAPACITORS; FERROELECTRIC RANDOM ACCESS MEMORY;

RANDOM ACCESS STORAGE;

EID: 0242526901     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A. Sheikholeslami and P.G. Gulak, "A Survey of Circuit Innovations in Ferroelectric Random-Access Memories," Proc. of the IEEE, Vol. 88, No. 5, pp. 665-689, May 2000.
2. H. Koike, T. Otsuki, T. Kimura, M. Fukuma, Y. Hayashi, Y. Maejima, K. Amanuma, M. Tanabe, T. Matsuki, S. Saito, T. Takeuchi, S. Kobayashi, T. Kunio, T. hase, Y. Miyasaka, N. shohota, and M. Takada, "A 60 ns 1 Mb nonvolatile ferroelectric memory with nondriven cell plate line write/read scheme", ISSCC Dig. Tech. papers, pp. 368-369, 1996.
3. H. Hirano, T. Honda, N. Moriwaki, T. Nakakuma, A. Inoue, G. Nakane, S. Chaya, and T. Sumi, "2-V/100-ns nonvolatile ferroelectric memory architecture with bitline-driven read scheme & nonrelaxation reference cell," Symp. VLSI Circuits Dig. Tech. Papers, pp. 48-49, 1996.
4. A. Sheikholeslami, P.G. Gulak, H. Takauchi, H. Tamura, H. Yoshika, and T. Tamura, "A pulse-based, parallel-element macromodel for ferroelectric capacitors," IEEE Trans. Ultrason., Ferroelect., Freq. Contr., Vol. 47, No. 4, pp. 784-791, July 2000.