Robust Memory Cell Capacitor using Multi-Stack Storage Node for High Performance in 90nm Technology and Beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 57-58

  Lee, Jaegoo ^a   Ahn, Yongseok ^a   Park, Yangkeun ^a   Kim, Minsang ^a   Lee, Dongjun ^a   Lee, Kyuhyun ^a   Cho, Changhyun ^a   Chung, Taeyoung ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; DATA REDUCTION; DIELECTRIC MATERIALS; LEAKAGE CURRENTS; ALUMINA; ALUMINUM OXIDE; CELLS; CYTOLOGY; DYNAMIC RANDOM ACCESS STORAGE; MEMORY ARCHITECTURE; SEMICONDUCTOR STORAGE;

MULTI-STACK STORAGE NODES;

DYNAMIC RANDOM ACCESS STORAGE; MECHANICAL STABILITY;

90NM TECHNOLOGIES; CAPACITOR STRUCTURES; CELL CAPACITANCE; CELL TECHNOLOGY; DRAM TECHNOLOGY; HIGH-LOW; LOW POWER APPLICATION; MEMORY CELL; PERFORMANCE; STORAGE NODES;

EID: 0141426825     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Y.K.Park et al., IEDM Tech. Dig., pp.819-822 (2002).
2. K.M. Kim et al., Symp. on VLSI Tech., p.7-8 (2001).
3. K.N.Kim et al., Symp. on VLSI Tech., p.10-11(2000).
4. Yongjik Park et al., IEDM Tech. Dig., pp.391-394 (2001).
5. Jaegoo Lee, et al., European Solid State Device Research Conference pp.571-574(2002).