Highly extendible memory cell architecture for reliable data retention time for 0.10μm technology node and beyond

European Solid-State Device Research Conference

Volumn , Issue , 2002, Pages 571-574

  Lee, Jaegoo ^a   Cho, Changhyun ^a   Lee, Juyong ^a   Shin, Sooho ^a   Lee, Jinwoo ^a   Kwak, Donghwa ^a   Lee, Kyuhyun ^a   Roh, Byunghyug ^a   Chung, Taeyoung ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CELLS; CYTOLOGY; DIGITAL STORAGE; MECHANICAL STABILITY; RANDOM ACCESS STORAGE; SURFACE CLEANING; SURFACE DEFECTS;

CELL ARCHITECTURES; CELL TRANSISTOR; CHANNEL DOPINGS; DATA RETENTION TIME; DYNAMIC RANDOM ACCESS MEMORY; JUNCTION LEAKAGE CURRENTS; SELF ALIGNED CONTACTS; SHORT-CHANNEL EFFECT;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84907698006     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2002.194995     Document Type: Conference Paper

References (5)

1. T. Hamamoto et al., "Well concentration: A novel scaling limitation factor derived from DRAM retention time and its modeling.", IEDM Tech. Dig., pp.915-918 (1995)
2. Hyung Soo Uh et al., "A Strategy for Long Data Retention Time of 512Mb DRAM with 0.12μm Design Rule.", Symp. On VLSI Tech., pp. 27-28 (2001)
3. Jooyoung Lee et al, "Novel Cell Transistor Using Retracted Si3N4-Liner STI for the Improvement of Data Retention Time in Gigabit Density DRAM and Beyond.", IEEE Trans. Electron Devices, vol.48, pp1152-1158, (2001)
4. Jaegoo Lee et al., "A Novel DRAM Technology using Dual Spacer and mechanically Robust Capacitor for 0.12μm DRAM and beyond.", European Solid State Device Research Conference pp.127-130 (2001)
5. Yongjik Park et al., "COB Stack Cell Technology beyond 100nm Technology Node.", IEDM Tech. Dig., pp.391-394 (2001)