On the design of IEEE compliant floating point units

IEEE Transactions on Computers

Volumn 49, Issue 5, 2000, Pages 398-413

  Even, Guy ^a   Paul, Wolfgang J ^b  

^a TEL AVIV UNIVERSITY   (Israel)

^b SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; LOGIC DESIGN; MULTIPLYING CIRCUITS;

COMPLIANT FLOATING POINT UNITS;

DIGITAL ARITHMETIC;

EID: 0034188008     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.859536     Document Type: Article

References (16)

1. J.T. Coonen, "Specification for a Proposed Standard for Floating Point Arithmetic," Memorandum ERL M78/72, Univ. of California, Berkeley, 1978.
2. G. Even, S.M. Mueller, and P.M. Seidel, "A Dual Mode IEEE Multiplier," Proc. Second IEEE Int'l Conf. Innovative Systems in Silicon, pp. 282-289, 1997.
3. D. Goldberg, "Computer Arithmetic," Computer Architecture: A Quantitative Approach, J.L. Hennessy and D.A. Patterson, eds., Appendix A, Morgan Kaufmann, 1990.
4. J.M. Feldman and C.T. Retter, Computer Architecture: a Designer's Text Based on a Generic RISC. McGraw-Hill, 1994.
5. I. Koren, Computer Arithmetic Algorithms, Prentice Hall, 1993.
6. "IEEE Standard for Binary Floating-Point Arithmetic," ANSI/IEEE Standard 754, 1985.
7. D. Matula, "Floating Point Representation," manuscript, May 1996.
8. S.M. Müller and W. Paul, "The Decomposition Theorem for IEEE Floating Point Rounding," manuscript, available at: http:// www.wjp.CS.Uni-SB.DE/∼smueller/publi.html.
9. S.M. Müller and W. Paul, "Complexity and Correctness of Computer Architectures," Springer, 2000.
10. A.R. Omondi, Computer Arithmetic Systems: Algorithms, Architecture and Implementations. Prentice Hall, 1994.
11. N. Quach, N. Takagi, and M. Flynn, "On Fast IEEE Rounding," Technical Report CSL-TR-91-459, Stanford Univ., Jan. 1991.
12. M.R. Santoro, G. Bewick, and M.A. Horowitz, "Rounding Algorithms for IEEE Multipliers," Proc. Ninth Symp. Computer Arithmetic, pp. 176-183, 1989.
13. P.-M. Seidel and G. Even, "How Many Logic Levels Does Floating-Point Addition Require?" Proc. 1998 IEEE Int'l Conf. Computer Design (ICCD '98): VLSI in Computers and Processors, pp. 142-149, Oct. 1998.
14. U. Sparmann, "Strukturbasierte Testmethoden für arithmetische Schaltkreise," PhD dissertation, Universität des Saarlandes, 1991.
15. S. Waser and M.J. Flynn, Introduction to Arithmetic for Digital Systems Designers. Holt, Reiner & Winston, 1982.
16. R.K. Yu and G.B. Zyner, "167 MHz Radix-4 Floating Point Multiplier," Proc. 12th Symp. Computer Arithmetic, vol. 12, pp. 149-154, 1995.