Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 μm CMOS process and implications for analog circuit design

IEEE Transactions on Nuclear Science

Volumn 50, Issue 4 II, 2003, Pages 915-920

  Terry, Stephen C ^a,b   Rochelle, James M ^b   Binkley, David M ^c,d   Blalock, Benjamin J ^a,b   Foty, Daniel P ^e   Bucher, Matthias ^f  

^a UNIVERSITY OF TENNESSEE   (United States)

^b Concorde Microsystems Inc ^*  (United States)

^c UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE   (United States)

^d Gilgamesh Associates ^*  (United States)

^e Gilgamesh Associates   (United States)

^f NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

Author keywords

Analog circuit design; BSIM3V3; CMOS modeling; EKV 2.6; Inversion coefficient; Transconductnce efficiency

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; MOSFET DEVICES; VOLTAGE MEASUREMENT;

ANALOG CIRCUITS;

PARTICLE DETECTORS;

EID: 0041926455     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2003.814588     Document Type: Conference Paper

References (17)

1. D. M. Binkley, B. S. Puckett, M. E. Casey, R. Lecomte, and A. Saoudi, "A power-efficient, low-noise, wideband, integrated CMOS preamplifier for LSO/APD pet systems," IEEE Tran. Nucl. Sci., vol. 47, pp. 810-817, June 2000.
2. M. Manghisoni, L. Ratti, V. Re, and V. Speziali, "Instrumentation for noise measurements on CMOS transistors for fast detector preamplifiers," IEEE Trans. Nucl. Sci., vol. 49, pp. 1281-1286, June 2002.
3. S. C. Terry, B. J. Blalock, L. K. Yong, B. M. Dufrene, and M. M. Mojarradi, "Complementary body driving - A low voltage analog circuit technique for SOI," Proc. 2002 IEEE Int. Silicon On Insulator Conf., pp. 80-82, Oct. 2002.
4. B. K. Swann, J. M. Rochelle, D. M. Binkley, B. S. Puckett, B. J. Blalock, S. C. Terry, J. W. Young, J. E. Breeding, K. M. Baldwin, and M. S. Musrock, "A custom mixed signal CMOS integrated circuit for high performance PET tomograph front-end applications," Proc. 2002 IEEE Nuclear Science Symp., Nov. 2000, to be published.
5. D. M. Binkley and D. P. Foty, "MOSFET modeling and circuit design: A methodology for transistor level analog CMOS design," in Proc. 37th Design Automation Conf. - Session 33, Los Angeles, CA, June 8, 2002.
6. D. M. Binkley, M. Bucher, and D. P. Foty, "Design oriented characterization of CMOS over the continuum of inversion level and channel length," in Proc. 7th Int. Conf. Electronics, Circuits, and Systems (ICECS'2K), Kaslik, Lebanon, Dec. 2000, pp. 161-164.
7. M. Bucher, C. Lallement, C. Enz, F. Theodoloz, and F. Krummenacher, "Scalable GM/I based MOSFET model," in Proc. 1997 Int. Semiconductor Device Research Symp., Charlottesville, VA, Dec. 1997, pp. 615-618.
8. E. Vittoz, "Micropower techniques," in Design on MOS VLSI for Telecommunications, J. Franca and Y. Tsividis, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1994.
9. D. M. Binkley, C. E. Hopper, S. D. Tucker, B. C. Moss, J. M. Rochelle, and D. P. Foty, "A CAD methodology for optimizing transistor current and sizing in analog CMOS design," IEEE Trans. Comput.-Aided Design Integrated Circuits Syst., vol. 22, pp. 225-237, Feb. 2003.
10. Y Tsividis and K. Suyama, "MOSFET modeling for analog circuit CAD: Problems and prospects," IEEE J. Solid-State Circuits, vol. 29, pp. 210-215, Mar. 1994.
11. B. Sheu, D. Scharfetter, P. Ko, and M. Jeng, "BSIM: Berkeley short channel IGFET model for MOS transistors," IEEE J. Solid-State Circuits, vol. SC-22, pp. 558-566, Aug. 1987:
12. D. P. Foty, MOSFET Modeling with Spice: Prentice-Hall, 1997.
13. C. Enz, F. Krummenacher, and E. Vittoz, "An analytical MOS model valid in all regions of operation and dedicated to low-voltage and low-current applications," J. Analog Integrated Circuits Signal Processing, vol. 8, pp. 83-114, July 1995.
14. M. Bucher, C. Lallement, C. Enz, F. Theodoloz, and F. Krummenacher. (1997) The EPFL-EKV MOSFET Model Equations for Simulation, Version 2.6. EPFL. [Online]. Available: http://legwww.epfl.ch/ekv/
15. W. Liu, X. Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu. (1999) BSIM3v3.2.2 MOSFET Model - Users Manual. Univ. California, EECS Dept., Berkeley, CA. [Online], Available: http://www-device.eecs.berkeley.edu bsim3/get.html
16. M. Bucher, D. Kazazis, F. Krummenacher, D. Binkley, D. Foty, and Y. Papananos, "Analysis of transconductances at all levels of inversion in deep submicron CMOS," in Proc. 9th IEEE Int. Conf. Electronics, Circuits, and Systems (ICECS 2002), vol. 3, Sept. 2002, pp. 1183-1186.
17. C. C. Enz and E. A. Vittoz, "CMOS low power analog circuit design," Emerging Technol.: Designing Low Power Digital Syst., pp. 79-133, 1996.