Characteristics of MOSFET with non-overlapped source-drain to gate

IEICE Transactions on Electronics

Volumn E85-C, Issue 5, 2002, Pages 1079-1085

  Lee, Hyunjin ^a   Chang, Sung Il ^a   Lee, Jongho ^b   Shin, Hyungcheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Wonkwang University   (South Korea)

Author keywords

50 nm MOSFET; Extended source drain; Non overlap; SCE

Indexed keywords

BAND STRUCTURE; CAPACITANCE MEASUREMENT; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC DEVICES; ELECTRIC FIELD EFFECTS; GATES (TRANSISTOR); PERMITTIVITY MEASUREMENT; SEMICONDUCTOR DEVICE STRUCTURES; SOLID STATE PHYSICS; THRESHOLD VOLTAGE;

DIELECTRIC SPACER; DRAIN CURRENT; DRAIN INDUCED BARRIER LOWERING; DRAIN VOLTAGE; INVERSION LAYER; SHORT CHANNEL EFFECTS; SUBTHRESHOLD SLOPE;

MOSFET DEVICES;

EID: 0036579146     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

1. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
2. Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs
3. 50 nm MOSFET with electrically induced source/drain extensions
4. GIDL currents in MOSFETs with high-k dielectric