Low-power CMOS PLL for clock generator

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2003, Pages

  Wu, Wen Chi ^a   Huang, Chih Chien ^a   Chang, Chih Hsiung ^b   Tseng, Nai Heng ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL CHIAYI UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

CLOCK GENERATORS;

TIMING CIRCUITS;

EID: 0038827209     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. H. C. Yang, L. K. Lance, and R. S. Co, "A Low-Jitter 0.3-165MHz CMOS PLL Frequency Synthesizer for 3V/Operation," IEEE J. of Solid-State Circuits, vol. 32, pp. 582-586, 1997.
3. Z-X. Zhang, H. Du, M. Lee, "A 360MHz 3V CMOS PLL with IV Peak-to-Peak Power-Supply-Noise Tolerance," IEEE Int. Solid-State Circuits Conference, FA.8.3, 1996.
4. S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi, and H. K. Lim, "A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL," IEEE J. of Solid-State Circuits, vol. 32, pp. 691-700, 1997.
5. R. C. Den Dulk, "Digital PLL Lock-Detection Circuit," Electronics Letters, Vol. 24, 880-882, 1988.
6. W. Rhee, "Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops," IEEE Int. Circuits and Systems Conference, Vol. 2, 545-548, 1999.