A dual channel ΣΔ ADC with 40MHz aggregate signal bandwidth

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Tabatabaei, Ali ^a   Onodera, Keith ^a   Zargari, Masoud ^a   Samavati, Hirad ^a   Su, David K ^a  

^a Atheros Communications   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FIR FILTERS; LOCAL AREA NETWORKS; MIM DEVICES; MOSFET DEVICES; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; TRANSFER FUNCTIONS; WIRELESS TELECOMMUNICATION SYSTEMS;

NOISE TRANSFER FUNCTION; QUANTIZATION NOISE SUPPRESSION; SPURIOUS FREE DYNAMIC RANGE; WIRELESS LOCAL AREA NETWORK;

DELTA SIGMA MODULATION;

EID: 0038645615     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. John Thomson, et al., "An Integrated 802.11a Baseband and MAC Processor," ISSCC Digest of Technical Papers, pp. 126-127, Feb. 2002.
2. Young-In Park, S. Karthikeyan, F. Tsay, E. Bartolome, "A 10b 100MSample/s CMOS Pipelined ADC with 1.8V Power Supply," ISSCC Digest of Technical Papers, pp. 130-131, Feb. 2001.
3. J. Vandenbussche, K. Uytenhove, E. Lauwers, M. Steyaert and G. Gielen, "A 8-bit 200 MS/s Interpolating/Averaging CMOS A/D Converter," CICC Digest of Technical Papers, pp. 445-446, May 2002.
4. A. Tabatabaei and B. A. Wooley, "A Two-Path Bandpass ΣΔ Modulator with Extended Noise Shaping," IEEE Journal of Solid-State Circuits, vol. 35, no. 12, pp. 1799-1809, December 2000.
5. R. H. Walden, "Analog-to-Digital Survey and Analysis," IEEE Journal of Selected Areas in Communications, vol. 17, no. 4, pp. 539-550, April 1999.