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Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2003, Pages 61-64

Damage-free SiO2/SiNx side-wall gate process and its application to 40nm InGaAs/InAIAs HEMT's with 65% InGaAs channel

(4) Kim, Dae Hyun a Kim, Suk Jin a Kim, Young Ho a Seo, Kwang Seok a

a Seoul National University (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON GAS; EXTRAPOLATION; GATES (TRANSISTOR); HIGH ELECTRON MOBILITY TRANSISTORS; MICROWAVE MEASUREMENT; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE STRUCTURES; SILICA; SILICON NITRIDE; TWO DIMENSIONAL; ARSENIC COMPOUNDS; DIELECTRIC MATERIALS; ETCHING; GALLIUM ARSENIDE; INDIUM; INDIUM COMPOUNDS; INDIUM PHOSPHIDE; PLASMA APPLICATIONS; PLASMA SOURCES; SEMICONDUCTING INDIUM; SILICON COMPOUNDS; SILICON OXIDES; SULFUR HEXAFLUORIDE;

HALL MOBILITY; INDIUM ALUMINUM ARSENIDE; SIDE-WALL GATE PROCESS; TWO DIMENSIONAL ELECTRON GAS DENSITY;

SEMICONDUCTOR DEVICE MANUFACTURE; HIGH ELECTRON MOBILITY TRANSISTORS;

DIELECTRIC LAYER; HEMTS; INDIUM GALLIUM ARSENIDE; INGAAS/INALAS; ITS APPLICATIONS; PLASMA PROPERTIES; PROCESS CONDITION; STRAINED CHANNELS;

EID: 0038487284 PISSN: 10928669 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (3)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.