Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 10, 1997, Pages 1101-1115

  Iris Bahar, R ^a   Cho, Hyunwoo ^a   Hachtel, Gary D ^a   Macii, Enrico ^a   Somenzi, Fabio ^a  

^a University of Colorado   (United States)

Author keywords

Decision diagrams; false paths; symbolic algorithms; timing analysis

Indexed keywords

EID: 33747079162     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.662674     Document Type: Article

References (30)

1. [1P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design. Norwell, MA: Kluwer Academic, 1991.
2. [2J. Benkoski, E. V. Meersch, L. Claesen, and H. De Man, Efficient algorithms for solving the false path problem in timing verification in ICCAD-87: IEEE Int. Conf. Computer Aided Design, Santa Clara, CA, Nov. 1987, pp. 44-47.
3. [3D. H. C. Du, S. H. C. Yen, and S. Ghanta, On the general false path problem in timing analysis in DAC-26: ACM/IEEE Design Automation CoJ., Las Vegas, NV, June 1989, pp. 555-560.
4. [4P. C. McGeer and R. K. Brayton, Efficient algorithms for computing the longest viable path in a combinational network in DAC-26: ACM/IEEE Design Automation Co/, Las Vegas, NV, June 1989, pp. 561-567.
5. [5H. C. Chen and D. H. C. Du, Path sensitization in critical paths IEEE Trans. Computer-Aided Design,12, pp. 196-207, Feb. 1993.
6. [6S. Devadas, K. Keutzer, and S. Malik, Delay computation in combinational logic circuits: Theory and algorithms in ICCAD-91: IEEE Int. Conf. Computer Aided Design, Santa Clara, CA, Nov. 1991, pp. 176-179.
7. [7H. Chang and J. A. Abraham, VIPER: An efficient vigorously sensitizable path extractor in DAC-30: ACM/IEEE Design Automation Conf., Dallas, TX, June 1993, pp. 112-117.
8. [8S. Devadas, K. Keutzer, S. Malik, and A. Wang, Computation of floating mode delay in combinational circuits: Practice and implementation in Int. Symp. Inform. Sei., Fukuoka, Japan, July 1992, pp. 88-75.
9. [9S. Devadas, H. F. Jyu, K. Keutzer, and S. Malik, Statistical timing analysis of combinational circuits in ICCD-92: IEEE Int. Conf. Computer Design, Cambridge, MA, Oct. 1992, pp. 38-13.
10. [10R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, Algebraic decision diagrams and their applications in ICCAD-93: ACM/IEEE Int. Conf. Computer Aided Design, Santa Clara, CA, Nov. 1993, pp. 188-191.
11. [11E. M. Sentovich, K. J. Singh, C. W. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, Sequential circuits design using synthesis and optimization in ICCD-92: IEEE Int. Conf. Computer Design, Cambridge, MA, Oct. 1992, pp. 328-333.
12. [12A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low-power CMOS digital design IEEE J. Solid-State Circuits,27, pp. 473-84, Apr. 1992.
13. [13C. Y. Tsui, M. Pedram, and A. M. Despain, Technology decomposition and mapping targeting low power dissipation in DAC-30: ACM/IEEE Design Automation Conf., Dallas, TX, June 1993, pp. 68-73.
14. [14V. Tiwari, P. Ashar, and S. Malik, Technology mapping for low power in DAC-30: ACM/IEEE Design Automation Conf., Dallas, TX, June 1993, pp. 74-79.
15. [15B. Lin and H. de Man, Low-power driven technology mapping under timing constraints in ICCD'93: IEEE Int. Conf. Circuits Design, Cambridge, MA, Oct. 1993, pp. 421-27.
16. [16F. Brglez and H. Fujiwara, A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran in ISCAS-85: IEEE Int. Symp. Circuits Syst., Kyoto, Japan, June 1985.
17. [17S. Yang, Logic synthesis and optimization benchmarks user guide version 3.0 Tech. Rep., Microelectron. Center of North Carolina, Research Triangle Park, NC, Jan. 1991.
18. [18F. N. Najm, Transition density, A stochastic measure of activity in digital Circuits in DAC-28: ACM/IEEE Design Automation Conf., San Francisco, CA, June 1991, pp. 644-649.
19. [19L. Classer and D. Dobberpuhl, The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985.
20. [20A. Ghosh, S. Devadas, K. Keutzer, and J. White, Estimation of average switching activity in combinational and sequential circuits in DAC29: ACM/IEEE Design Automation Conf., Anaheim, CA, June 1992, pp. 253-259.
21. [21R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, Algebraic decision diagrams and their applications Int. Rep., VLSI/CAD Res. Group, Dep. Elect. Comput. Eng., Univ. Colorado, Boulder, Apr. 1993.
22. [22S.-W. Jeong, B. Plessier, G. D. Hachtel, and F. Somenzi, Variable ordering for binary decision diagrams in EDAC-92: IEEE European Conf. Design Automation, Brussels, Belgium, Mar. 1992, pp. 447-151.
23. [23H. Fujii, G. Ootomo, and C. Hori, Interleaving based variable ordering methods for ordered binary decision diagrams in ICCAD-93: ACM/IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 1993, pp. 38-1.
24. [24M. Fujita, Y. Matsunaga, and T. Kakuda, On variable ordering of binary decision diagrams for the application of multi-level logic synthesis in EDAC-9I: IEEE European Conf. Design Automation, Amsterdam, The Netherlands, Feb. 1991, pp. 50-54.
25. [25N. Ishiura, H. Sawada, and S. Yajima, Minimization of binary decision diagrams based on exchanges of variables in ICCAD-91: ACM/IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 1991, pp. 472-75.
26. [26R. Rudell, Dynamic variable ordering for ordered binary decision diagrams in ICCAD-93: ACM/IEEE Int. Conf. Computer Aided Design, Santa Clara, CA, Nov. 1993, pp. 42-7.
27. [27S. Panda, F. Somenzi, and B. Plessier, Symmetry detection and dynamic variable ordering of decision diagrams in ICCAD-94: ACM/IEEE Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1994.
28. [28O. Coudert, C. Berthet, and J. C. Madre, Verification of sequential machines using boolean functional vectors in IFIP Int. Workshop Appl. Formal Methods for Correct VLSI Design, Leuven, Belgium, Nov. 1989, pp. 111-128.
29. [29S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, The transduction method-Design of logic networks based on permissible functions IEEE Trans. CompuL,38, pp. 1404-1424, Oct. 1989.
30. [30A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Circuit structure relations to redundancy and delay: The KMS algorithm revisited in DAC-29: ACM/IEEE Design Automation Conf., Anaheim, CA, June 1992, pp. 245-248.