An offset cancellation bit-line sensing scheme for low-voltage DRAM applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 154-155+455+151

  Hong, Sang Hoon ^a   Kim, Si Hong ^a   Kim, Se Jun ^a   Wee, Jae Kyung ^a   Chung, Jin Yong ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SYSTEMS; FEEDBACK; SEMICONDUCTING SILICON;

BIT-LINE SENSE AMPS (BLSA);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036116459     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Offset compensating bit-line sensing scheme for high density DRAM's
2. Multiple twisted dataline techniques for multigigabit DRAM's