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Volumn 5, Issue , 2003, Pages

Analysis of output ripple in multi-phase clocked charge pumps

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC POTENTIAL; MOS CAPACITORS; MOSFET DEVICES;

EID: 0038082048     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (6)
  • 3
    • 0035472555 scopus 로고    scopus 로고
    • A supply-noise-insensitive MOS PLL with a voltage regulator using DC-DC capacitive converter
    • Oct.
    • C.-H. Lee, K. McClellan, and J. Choma Jr., "A Supply-Noise-Insensitive MOS PLL With a Voltage Regulator Using DC-DC Capacitive Converter," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1453-1463, Oct. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.10 , pp. 1453-1463
    • Lee, C.-H.1    McClellan, K.2    Choma J., Jr.3
  • 4
    • 0035060358 scopus 로고    scopus 로고
    • A 1V 1mW CMOS front-end with on-chip dynamic gate biasing for a 75Mb/s optical receiver
    • Feb.
    • K. Phang and D. Johns, "A 1V 1mW CMOS Front-End with On-chip Dynamic Gate Biasing for a 75Mb/s Optical Receiver," IEEE Int. Solid-State Circ. Conf. Dig. Tech. Papers, pp. 218-219, Feb. 2001.
    • (2001) IEEE Int. Solid-state Circ. Conf. Dig. Tech. Papers , pp. 218-219
    • Phang, K.1    Johns, D.2
  • 5
    • 0032028335 scopus 로고    scopus 로고
    • High-efficiency CMOS Voltage Doubler
    • March
    • P. Favrat, P. Deval, and M. J. Declercq, "High-Efficiency CMOS Voltage Doubler," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, March 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.3 , pp. 410-416
    • Favrat, P.1    Deval, P.2    Declercq, M.J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.