A low-voltage CMOS filter for hearing aids using dynamic gate biasing

Canadian Conference on Electrical and Computer Engineering

Volumn 1, Issue , 2001, Pages 183-188

  Pylarinos, L ^a   Wong, N W ^a   Phang, K ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); HEARING AIDS; MOSFET DEVICES; TRANSCONDUCTANCE; TRANSFER FUNCTIONS; TUNING;

CONTINUOUS TIME FILTERS; DYNAMIC GATE BIASING;

ACTIVE FILTERS;

EID: 0034850827     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. High-efficiency CMOS voltage doubler
2. A 1V 1mW CMOS front-end with on-chip dynamic gate biasing for a 75Mb/s optical receiver
3. Low-voltage analog CMOS filter design
4. An adaptive analog continuous-time CMOS biquadratic filter
5. A family of differential NMOS analog circuits for a PCM codec filter chip
6. A high-performance micropower switched-capacitor filter
7. On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique
8. A switched capacitor double voltage generator
9. MOS charge pumps for low-volt-age operation
10. Switched-capacitor building blocks for adaptive systems
11. A single-chip hearing aid with one volt switched-capacitor filters
12. Charge pump for optimal dynamic range filters