Long-term power minimization of dual-νΤ CMOS circuits

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 323-327

  Kim, Suhwan ^a   Shin, Youngsoo ^a   Kosonocky, Stephen ^a   Hwang, Wei ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; THRESHOLD VOLTAGE; VOLTAGE SCALING;

CARRY LOOK-AHEAD ADDER; CMOS CIRCUITS; DUAL THRESHOLD VOLTAGE; NOVEL DESIGN METHODOLOGY; POWER GATINGS; POWER MINIMIZATION; SYSTEM-LEVEL POWER MANAGEMENT; TOTAL POWER DISSIPATION;

ELECTRIC LOSSES;

EID: 0038062415     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158079     Document Type: Conference Paper

References (6)

1. Z. Chen, C. Diaz, J. D. Pìummer, M. Cao, and W. Greene, "0.18 um dual Vt MOSFET process and energy-delay measurement," in Proceedings of IEEE International Electron Devices Meeting, 1996, pp. 851-854.
2. Q. Wang and S. Vrudhu!a, "Efficient procedures for minimizing the standby power in dual VT CMOS circuits," in Proceedings of International Workshop on Power and Timing Modeling. Optimization and Simulation, Oct. 1998.
3. Q, Wang and S. Vrudhula, "Static power optimization of deep submicron CMOS circuits for dual VT technology." in Proceedings of the International Conference on Computer Aided Design, 1998, pp. 490-494.
4. P. Pant, R. K. Roy, and A. Chatterjee, "Dual-threshold voltage assignment with Transistor sizing for low power CMOS circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9. no. 2, pp. 390-394, Apr. 2001.
5. V. Tiwari, R. Donnelly, S. Malik, and R. Gonzalez, "Dynamic power management for microprocessors: A case study," in Proceedings Tenth International Conference on VLSI Design, Jan. 1997. pp. 185-192.
6. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamda, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Sold-Staie Circuits, vol. SC-30, no. 8. pp. 847-854, Aug. 1995.