Room temperature bonding of ultra-fine pitch and low-profiled Cu electrodes for bump-less interconnect

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 848-852

  Shigetou, A ^a   Itoh, T ^a   Matsuo, M ^b   Hayasaka, N ^b   Okumura, K ^a   Suga, T ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; CURRENT DENSITY; ELECTRIC RESISTANCE MEASUREMENT; ELECTRODES; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; OPTICAL INTERCONNECTS; RELIABILITY;

BUMP LESS INTERCONNECTS; CHAIN RESISTANCE MEASUREMENT; CHEMICAL MECHANICAL PLANARIZATION; LOW PROFIELD COPPER ELECTRODES; REACTIVE ION BEAM ETCHING; SURFACE ACTIVATED BONDING METHOD; ULTRA FINE PITCH;

SOLDERING;

EID: 0038012488     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Y. Tomita, M. Tago et al., Proc. IEEE, EMAP 2001, pp. 107-114
2. K. Takahashi, M. Hoshino, H. Yonemura et al., Proc. 51st IEEE, ECTC, Orlando, FL, May, 2001, pp. 541-546.
3. T. Suga, K. Otsuka, Proc. 51st IEEE, ECTC, Orlando, FL, May, 2001, pp. 1003-1008.
4. H. Takagi, K. Kikuchi, et al., appl. Phys. lett., 68 (1996) pp. 2222-2224.
5. A. Shigetou, N. Hosoda, T. Itoh and T. Suga, Proc. 51st IEEE, ECTC, Orlando, FL, May, 2001, pp. 755-760