Planar metallization interconnected 3-D multi-chip module

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 1090-1094

  Liang, Zhenxian ^a   Van Wyk, J D ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELECTRIC CURRENTS; ELECTRODES; ELECTRONICS PACKAGING; INTERCONNECTION NETWORKS;

HIGH DENSITY INTERCONNECT; INTEGRATED POWER ELECTRONICS MODULES; UNDER BUMP METALLIZATION; WAFER-LEVEL CHIP SIZE PACKAGING;

MULTICHIP MODULES;

EID: 0038012416     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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