Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide

IEEE Electron Device Letters

Volumn 24, Issue 3, 2003, Pages 174-176

  Lee, Seok Woo ^a   Kim, Eugene ^a   Han, Sang Soo ^a   Lee, Hye Sun ^a   Yun, Duk Chul ^a   Lim, Kyoung Moon ^a   Yang, Myoung Su ^a   Kim, Chang Dong ^a  

^a LG Display Co Ltd   (South Korea)

Author keywords

Gate oxide integrity; MOS; PECVD SiO2; Post annealed gate oxide; TFT

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTERFACES (MATERIALS); MOS CAPACITORS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; POLYSILICON; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SILICA; SILICON WAFERS; SUBSTRATES;

DEEP LEVEL INTERFACE STATE; GATE OXIDE FILM; GATE OXIDE INTEGRITY; POST-ANNEALING GATE OXIDE;

THIN FILM TRANSISTORS;

EID: 0037938612     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.811398     Document Type: Letter

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