Simulation of nonequilibrium thermal effects in power LDMOS transistors

Solid-State Electronics

Volumn 47, Issue 8, 2003, Pages 1265-1273

  Raman, A ^a   Walker, D G ^a   Fisher, T S ^a  

^a VANDERBILT UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MOS DEVICES; PHONONS; SILICON ON INSULATOR TECHNOLOGY; THERMAL EFFECTS;

PHONON SCATTERING;

MOSFET DEVICES;

EID: 0037936539     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00066-2     Document Type: Article

References (19)

1. Shenai K. Optimally scaled low voltage vertial power DMOSFETs for high frequency power switching applications. IEEE Trans. Electron Devices. 37:1990;1141.
2. Trivedi M., Khandelwal P., Shenai K. Performance modeling of RF power MOSFETs. IEEE Trans. Electron Devices. 46(8):1999;1794.
3. Baliga BJ. Revolutionary innovations in power discrete devices. In: International Electron Devices Meeting. 1980. p. 102-105.
4. Versari R, Pieracci A, Manzini S. Hot carrier reliability in submicrometer LDMOS transistors. In: International Electron Devices Meeting. 1997. p. 371.
5. Manzini S, Contiero C. Hot electron induced degradation in high voltage submicron DMOS transistors. In: Proc IEEE ISPSD. 1996. p. 75.
6. Versari R., Pieracci A. Experimental study of hot-carrier effects in LDMOS transistors. IEEE Trans. Electron Devices. 46(6):1999;1228.
7. Ferry D.K. Semiconductors. 1991;Macmillan Publishing Company, New York.
8. Apanovich Y., Blakey P., Cottle R., Lyumkis E., Polsky B., Shur A.et al. Numerical simulation of submicrometer devices including coupled nonlocal transport and nonisothermal effects. IEEE Trans. Electron Devices. 42(5):1995;890.
9. Wachutka G.K. Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling. IEEE Trans. Comput. Aided Design. 9(11):1990;1141.
10. Lai J., Majumdar A. Concurrent thermal and electrical modeling of sub-micrometer silicon devices. J. Appl. Phys. 79(9):1996;7353.
11. Majumdar A., Fushinobu K., Hijikata K. Effect of gate voltage on hot-electron and hot-phonon interaction and transport in a submicrometer transistor. J. Appl. Phys. 77(12):1995;6686.
12. Leung Y.K., Paul A.K., Goodson K.E., Plummer J.D., Wong S.S. Heating mechanisms of LDMOS and LIGBT in ultrathin SOI. IEEE Electron Device Lett. 18(9):1997;414.
13. Silvaco International, Atlas Users's Manual - Device Simulation Software. Santa Clara, California, 1998.
14. Lim H.T., Udrea F., Garner D.M., Milne W.I. Modeling of self-heating effect in thin SOI and partial SOI power devices. Solid State Electron. 43:1999;1267.
15. Perugupalli P., Trivedi M., Shenai K., Leong S.K. Modeling and characterization of an 80v silicon LDMOSFET for emerging RFIC applications. IEEE Trans. Electron Devices. 45(7):1998;1468.
16. Sverdrup P.G., Ju Y.S., Goodson K.E. Sub-continuum simulations of heat conduction in silicon-on-insulator transistors. J. Heat Transf. 123:2001;130.
17. Tien C.L., Majumdar A., Gerner F.M. Microscale energy transport. 1998;3-94 Taylor & Francis.
18. Walker DG, Fisher TS, Ralston-Good J, Schrimpf RD. Coupled phonon energy transport in semiconductor devices. In: 2000 ASME International Mechanical Engineering Congress and Exhibit, vol. 2. Orlando, FL, 2000. p. 325-330.
19. Langtangen H.P. Computational partial differential equations: numerical methods and diffpack programming. 1999;Springer, Germany.