Bonding-pad-oriented on-chip ESD protection structures for ICs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2003, Pages

  Feng, H ^a   Zhan, R ^a   Chen, G ^a   Wu, Q ^a   Guang, X ^a   Xie, H ^a   Wang, A ^a  

^a Illinois Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC POTENTIAL; ELECTROSTATICS; THYRISTORS;

LOW-VOLTAGE SILICON CONTROLLED RECTIFIERS (LVSCR);

CMOS INTEGRATED CIRCUITS;

EID: 0037812910     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Wang A., Feng H., Gong K., Zhan R. and Stine J., "On-chip ESD protection design for ICs", J. Microelectronics, Elsevier Science, Vol. 32/9, August 2001, pp.733.
2. Anderson W., Gonzalez W., Knecht S. and Fowler W., "ESD protection under wire bonding pads", Proc. EOS/ESD Symp., 1999, pp.88.
3. Chou K. and Chen M., "ESD protection under grounded-up bond pads in 0.13μm eight-level metal CMOS process technology", IEEE EDL., Vol. 22, No. 7, July 2001, pp.342.